feat(kernel): brief echo-back gate (plan-pipeline-addenda A1)

New brief_echo stage before the planner in role_pipeline: the model restates
the analyst brief as a structured artifact, and a deterministic gate
(checkBriefEcho, opt-in via brief_echo=true) diffs the restatement against the
original brief. On divergence — dropped requirements (Jaccard coverage < 0.34)
or hallucinated files — it emits BriefEchoMismatchEvent and fails the stage
retryably, so a misread brief never reaches plan generation.

The diff (BriefEchoDiff) is a pure function of two recorded artifacts, so it is
replay-safe and records no observation; the event fires only on mismatch, for
audit. Symbols are recorded but non-blocking in v1. Mirrors the groundBrief-
References gate. role_pipeline only; freestyle_planning wiring is a follow-up.

Runtime install (like research): copy brief_echo.json + brief_echo.md and the
[[artifacts]] block into ~/.config/correx.

This commit is contained in:

kami

2026-06-14 19:43:15 +04:00

parent 40245583e5

commit bcc59d2164

12 changed files with 520 additions and 7 deletions

									
										examples/workflows/artifacts.config.toml
									
		+5
		
												View File
												
				@@ -29,6 +29,11 @@ id = "review_report"

				schema_path = "schemas/review_report.json"

				llm_emitted = true

				[[artifacts]]

				id = "brief_echo"

				schema_path = "schemas/brief_echo.json"

				llm_emitted = true

				[[artifacts]]

				id = "execution_plan"

				schema_path = "schemas/execution_plan.json"